Press Release


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August 20, 2001



-Reference-

Sony Develops Low Power Consumption LSI for "Network Handycam IP"



Tokyo, Japan - Sony Corporation today announced a MPEG CODEC LSI [CXD2890] with DRAM process and a camera signal processing LSI [CXD1451] for a new format MICROMV "Network Handycam IP" camcorder.

Sony positions semiconductors as a key device that adds significant value to its electronics products and is currently pursuing various strategies to enhance this policy such as strengthening design and production facilities. Sony's product divisions and semiconductor divisions collaborated to facilitate the design and development of the system LSI, one of the most important components for consumer electronic products/digital video cameras.

With 0.18um DRAM logic processing and circuitry technologies, the newly developed LSIs, [CXD2890] and [CXD1451] can realize a 1.5V single power voltage on the logic circuit and DRAM, which enables both the size of the chip and the energy consumption to be significantly reduced.

The [CDX2890] is a MPEG signal processing LSI with 48mega bit DRAM which performs real time encode and decode processing of MPEG2 based on MPEG2 MP@ ML. With a 1.5V single driving voltage, it achieves low power consummation at approximately 170mW in encoding mode.

The [CXD1451] is a camera signal processing LSI, which consolidates the camera signal processing for picture signals transmitted from CCD into a single chip with a 12 mega bit DRAM. Consequently, it realizes 1.5V single power voltage and power consumption at approximately 300mW in camera recording mode.

The two newly developed LSIs play key roles in the new "Network Handycam IP" [DCR-IP7] which is scheduled to be sold in the Japanese market from October 2001.

<Main features>

CXD2890 CXD1451
Function MPEG2 Video Codec(Simultaneous operation of Encoding/Decoding, MPEG1/2 conversion) 1 Chip, Camera signal ProcessingAnalog Interface
DRAM 48M bit 12M bit
Gate 1500K 1850K
Operating frequency External : 33.75MHz
Internal : 67.5MHz
External : 13.5MHz
Internal : 13.5MHz
Power supply voltage Logic :1.5V
DRAM :1.5V
Logic :1.5V
DRAM :1.5V
Process 0.15um DRAM logic process 0.18um DRAM logic process
(Analog optional)
Power Consumption 170mW (encoding)
90mW (decoding)
340mW (camera recording)
Package Ultra small LFLGA Package
328 pins, 0.5mm pitch, thickness 1.2mm
Ultra small LFLGA Package
308 pins, 0.5mm pitch, Thickness 1.2mm