Press Release

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February 8, 2000

Sony Develops Noise Reduction Technologies to
Enhance Image Quality of CMOS Image Sensors

(Tokyo, Japan) - Sony Corporation today announced the development of technologies that enhance the image quality of CMOS (Complementary Metal Oxide Semiconductor) image sensors. By utilizing Sony's proprietary "DRSCANTM" noise reduction technology and "HADTM" dark current suppression technology, the fixed pattern noise of CMOS image sensors can be substantially reduced.
The above technologies were announced at the ISSCC (International Solid State Circuit Conference) in San Francisco on February 7th.

In light of the approaching digital network era, CMOS image sensors characterized by their low power consumption can serve as image capturing device for portable devices such as the PDA (Personal Digital Assistant). However, CMOS image sensors are subject to fixed pattern noise that results from the differing characteristics of individual transistors, as well as dark current that occurs regardless of the amount of absorbed light. Research into finding a solution to these problems has been conducted to improve the image quality of CMOS image sensors.

"DRSCANTM" technology removes fixed pattern noise that results from the differing characteristics of individual transistors. A single noise-cancellation circuit sequentially removes noise that is included in each pixel signal, thereby suppressing the varying noise level that could not be removed by conventional line-correction method.

"HADTM" technology, applied from CCD image sensors, suppresses fixed pattern noise that results from unwanted dark current that occurs regardless of the amount of absorbed light. By fabricating a hole-accumulation layer below the surface of the image sensor, dark current can be suppressed at source.
By combining these two technologies, fixed pattern noise can be substantially suppressed to improve signal-to-noise level by approximately 25 times.

In addition to improving image quality, image lag has also been suppressed by optimizing pixel construction. By adopting L-shaped gate for "HADTM", electrons in the pixel can be effectively transferred for lag-free image.

Sony has successfully developed a prototype CMOS image sensor (diagonal 6mm (Type 1/3) 330,000 pixels) that utilizes "DRSCANTM" and "HADTM" technologies. Sony will now work to commercialize the CMOS image sensors for application in products that require low power consumption.

*"DRSCANTM (Dot sequential Readout System with Current Amplified signal output Noise reduction circuit)" and "HADTM (Hole Accumulation Diode)" are trademarks of Sony Corporation.

Main Specifications of Prototype

Semiconductor Process :0.35um CMOS
Image Size:diagonal 6mm (1/3 type)
Number of Effective Pixels:330,000 pixels 659(H) X 494(V)
Pixel Size:7.4um (H) X 7.4um (V)
Sensitivity (F5.6):0.52V/lx-s
Power Voltage:3.3V single-source
Power Consumption:31mW
Dark Current:370 pico-ampere/cm2 (room temperature)
Dynamic Range:53dB
Chip Size:5.84mm (H) X 5.01mm (V)
Image Lag:Below measuring limit