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Sony's "Cell Broadband Engine" (Cell/B.E.) provides advanced broadband media processing with supercomputer performance. This high-performance processor was jointly developed by Sony, Sony Computer Entertainment, Toshiba and IBM. The superb computing performance of Cell/B.E. was achieved by combining IBM's semiconductor technology and advanced multiprocessing technology used in high-performance servers with computer systems entertainment technology provided by the Sony Group and semiconductor technology by Toshiba. The starting point for the development project was the processor designed for use in "PLAYSTATION 3." However, Cell/B.E. was designed from the outset for versatility and is expected to be used in a wide range of applications, including not only AV equipment, such as televisions and HD recorders, but also servers.

The Structure of Cell/B.E.
SPE with Advanced Security Functions
Giant Computer System Based on Grid Computing
The Future of the Technology
Technology Showcased at SIGGRAPH2007

The Structure of Cell/B.E.

Cell/B.E. is a heterogeneous multicore processor consisting of two kinds of processor cores --- PowerPC Processor Elements (PPEs) to handle general processing and Synergistic Processor Elements (SPEs) multimedia processing --- on a single CPU die. Cell/B.E. is designed to support multiple SPEs, and the basic configuration is one PPE with eight SPEs. The number of transistors integrated under this configuration is an astounding 234 million. The operating frequency delivers a clock speed in excess of 4GHz (*). The result is awesome processing capacity.

Cell/B.E. used in PLAYSTATION 3 consists of one PPE and seven SPEs. (Eight SPEs are physically present, but only seven are used.) The system has a clock speed 3.2GHz and floating-point operation performance in excess of 200GFLOPS.

* Based on an evaluation carried out during initial testing.

PPE
PowerPC Processor Element

PPU (PowerPC Processor Unit)
A processor core based on the PowerPC

L1 (L1 Cache)
This extremely fast memory is used as temporary storage for instructions and data to be processed by the PPU in order to offset a difference between the processing speed of the PPU and the transfer speed of the main memory. It consists of the L1 data cache (32 kilobytes) and L2 instruction cache (32 kilobytes), making a total of 64 kilobytes.

L2 cache
Like the L1 cache, this memory is used as temporary storage for data to be processed by the PPU. It is slower than the L1 cache, but its capacity is higher at 512 kilobytes, and it is used to make up for any shortfall in the capacity of the L1 cache.

SPE
Synergistic Processor Element

SPU (Synergistic Processor Unit)
This processor core forms the heart of the SPE

LS (Local Store)
This local memory is used to store instructions and data to be processed by SPE. Its capacity is 256 kilobytes. SPE can provide robust security through its ability to prevent external access to the LS.

MFC (Memory Flow Controller)
This controls SPE memory access. A DMA controller is also embedded to allow main memory access without the need for an external controller.

EIB
Element Interconnect Bus
The on-chip internal bus that handles communication between Cell/B.E. elements.

Flex IO
The I/O controller

Memory Interface Controller
The memory controller

IIC
Internal Interrupt Controller

Bridge Chip
This controller chip provides external I/O.

GPU
This is the graphic controller. An "RSX" GPU is connected within PLAYSTATION 3.

XDR DRAM
This high-speed DRAM was developed by Rambus Inc. It operates at 3.2GHz and provides 25.6GB/s of bandwidth.

I/O
Abbreviation for Input/Output

■PowerPC Processor Element: The PowerPC Processor Element (PPE) is the general-purpose processor for the PowerPC architecture. Its main role is to run the operating system and manage SPE tasks. The PPE is equipped with 32 kilobytes of L1 data cache, 32 kilobytes of L1 instruction cache, and 512 kilobytes of L2 cache. It is also capable of simultaneous multithreading (SMT) and can execute two threads at the same time.
■Synergistic Processor Element: The Synergistic Processor Element (SPE) is used mainly to process multimedia content, such as video and audio. This SIMD processor can simultaneously apply the same type of operation to multiple data with a single instruction and is capable of handling four 32-bit single-precision floating-point operations, two 64-bit double-precision floating-point operations, or four 32-bit integer operations at the same time. It is equipped with 128 128-bit registers and a 256 kilobyte "local store" for instruction and data storage. The Memory Flow Controller (MFC) is a memory control unit equipped with a DMA controller (*), allowing the SPE to access main memory independently without going through an external controller.; * This provides communication control for DMA transfers when memory, etc., on the motherboard transfers data without going through the CPU.
■Memory Interface: Cell/B.E. has dual memory interface channels to support high-performance XDR DRAM. The XDR DRAM used in PLAYSTATION 3 operates at 3.2GHz and provides 25.6GB/s of bandwidth.
■I/O Controller: The I/O controller is connected to an external drawing processor (the "RSX" (*) in PLAYSTATION 3) or an external I/O bridge, which is used to connect general-purpose storage devices.; * A graphic processor jointly developed by Sony Computer Entertainment Inc. and NVIDIA Corporation
■Element Interconnect Bus: The PPE, SPE, memory interface and I/O controller (which are all imbedded in Cell/B.E.) are connected to an internal bus called the "Element Interconnect Bus" (EIB). The EIB has a unique structure in the form of four 16-byte rings, with data moving clockwise in two and counter-clockwise in the other two. The advantage of this ring structure is that it facilitates SPE expansion and the provision of bandwidth. The maximum data bandwidth is 96 bytes per cycle (307.2 gigabytes per second at 3.2GHz).

SPE with Advanced Security Functions

SPEs protect copyrights by preventing access to data held in the local store. If an SPE shuts off access to the local store, neither the PPE nor other SPEs will be able to access the local store until that SPE has completed all processing and releases the local store. This feature ensures excellent security since data being processed are totally protected from external access. It was designed to support digital rights management (DRM), including not only the system used for games, but also the AACS technology implemented on Blu-Ray Discs. It is this robust security that makes Cell/B.E. ideal for use on a wide variety of multimedia equipment in addition to PLAYSTATION 3.

Giant Computer System Based on Grid Computing

From the outset, Cell/B.E. was conceived as a component device that could be used standalone as well as part of a giant grid computing system created by linking individual Cell/B.E. units through LANs or across the internet. This approach leads to major improvements in system performance without the need to improve the performance of individual units. A grid computing system based on Cell/B.E. has already been implemented using PLAYSTATION 3. PLAYSTATION 3 consoles are now participating in Folding@home, a distributed computing project established by Stanford University to study protein folding. This project has immense computing and analysis requirements, but thanks to parallel distributed processing carried out over numerous PLAYSTATION 3s, the overall analysis time has been reduced significantly. According to the Guinness Book of Records, Folding@home is the world's most powerful distributed computing network. The massive processing power of Cell/B.E. has helped to make this possible.

Figure 2: Folding@home

The Future of the Technology

Figure 3: A magnified view of Cell

Cell/B.E. was initially manufactured using a 90nm process. However, a 65nm process has been used since 2007. The smaller process has not only reduced power consumption, but has also resulted in lower costs, since more chips can be manufactured from a single silicon wafer. These improvements mean that Cell/B.E. can easily be used on a wide range of devices in addition to PLAYSTATION 3. The Sony Group plans to develop various other applications for Cell.

Technology Showcased at SIGGRAPH2007

SIGGRAPH2007(*), Sony exhibited a Cell Computing Board equipped with the Cell/B.E. high-performance microprocessor and "RSX" graphics processor. Designed for compactness and low power consumption, the board is capable of high-speed operations, enabling it to carry out large-scale computing extremely rapidly. With this technology, Sony has demonstrated the potential for new solutions for multimedia computing applications that require massive computing power, ranging from computer graphics and other types of image processing to computing for science and technology.

*	SIGGRAPH (Special Interest Group on Computer Graphics) is the worlds' biggest international conference on computer graphics and interactive techniques. Held in the United States, it is sponsored by the Association for Computing Machinery.

Vol.4 Cell-The Dream Processor

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