*1:CMOS image sensors in a stacked structure that layer the pixel section containing back-illuminated structure pixels onto semiconductor chips containing the circuit for signal processing, in contrast to the supporting substrates used in conventional back-illuminated CMOS image sensors.
*2:The mastering process refers to the manufacture of photodiodes and wiring processes for stacked CMOS image sensors. The layering process refers to the layering of semiconductor chips containing back-illuminated structure pixels on top of semiconductor chips containing the circuit for signal processing.
*3:A separate investment of approximately 105 billion yen, intended to bolster production capacity from the current level of approximately 60,000 wafers per month to the level of approximately 80,000 wafers per month by the end of June 2016, was previously announced on February 2, 2015.
*4:This total production capacity (300mm wafer basis) includes the output of foundry operations to which Sony outsources a part of the manufacturing process. For the purposes of calculating total production capacity, the capacity of 200mm wafer production lines at the Kagoshima Technology Center and Nagasaki TEC are converted into equivalent amounts in terms of 300mm wafer production.