Interface Circuit Technology |
| . |
. |
The second characteristic of the MCL
technology lies in the miniaturization and
test circuit technologies for the I/O circuits
in the inter-chip interface.
Figure 6 shows the block diagram for the
interface circuit. Due to the use of tiny
microbumps for connection between pairs
of chips, it is possible to use, in the interface
sections, buffers that are smaller than
the external I/O circuits used in current
LSIs and that have sizes similar to the chip
internal buffers. This means that MCL can
achieve lower power operation than current
SiP technology.
ESD protection diodes that protect the circuits
from electrical damage during processing
and test circuits are also inserted
at each connection node. The added test
circuits are used to perform testing up to
the buffers before and after the chip
microbumps before Chip on Chip connection
and to perform testing through the
original test circuits and microbumps after
connection. This increases the number
of units that pass testing and reduces
total costs.
By applying the above technologies, Sony
is able to use more than 1000 signal lines
(microbumps) in the connection between
chips without reducing yields.
Compared to chip connection using current
wire bonding, the number of inter-chip
connections can be increased by
more than a factor of ten and the connection
spacing can be reduced to less than
1/10 previous distances. Sony has
achieved multi-pin connections and high-speed
wide-bandwidth data transfers that
could not be achieved up to now using
the SiP technology. (See figure 7.) |
|
|
Industry-Leading Achievements
in Mass Production |
| . |
. |
This MCL technology was adopted in the
CPU for the Sony PSP® and the Sony
Semiconductor Kyushu Corporation Oita
Technology Center is leading the industry
in mass production using this technology.
In the current SoC version, a 90 nm embedded
DRAM process that embeds both
a CPU and 4MB of DRAM in a single
chip was used, but in the MCL version, a
4MB DRAM chip created in a 0.18 μm
process was mounted using Chip on Chip
connection on a CPU chip created in a 90
nm pure logic process. Manufacturing the
CPU and DRAM as two chips made it
possible to optimize the designs, processes,
and number of process steps for
each of the chips independently. That is
to say, it became possible to select the
lowest cost process for each chip without
having to use a finer fabrication process
than was actually required.
The CPU and DRAM chips were connected
with approximately 1400
microbumps, and a maximum bandwidth
of 21 GB/s was achieved.
Also, the thickness of each of the chips
was held to under 150 μm, and despite
packaging two chips (CPU and DRAM)
in a single package, the package thickness
was the same as that for the SoC
(single chip) version. Furthermore, compatibility
with the end product was assured
by designing the package external
output pins to be the same as those in the
SoC version.
Although heat generation due to implementation
in two chips was a concern, this
was verified to be about the same as that
for the SoC version.
As a result, switching to the MCL technology
achieved the same bandwidth and
power consumption as the SoC version,
but reduced the chip size by approximately
27% as shown in figure 8, improved
yield, and reduced manufacturing
costs. |
|
|
Future Developments |
| . |
. |
In addition to the PSP® LSI discussed
here, Sony plans to deploy this newly-developed
MCL technology to new areas
where high performance and low power
are required.
Sony is also considering providing an assembly
subcontracting service using the
technologies developed here so that our
customers can achieve competitive LSIs.
This will enable Sony to propose solutions
that respond to customer needs and provide
new added values as well.
You can look forward to continuing advances
from Sony in the semiconductor
assembly technology fostered in our efforts
at end product miniaturization and
thickness reduction.
* PSP® and “PlayStation Portable” are
registered trademarks of Sony Computer
Entertainment Inc. |
|
 |
See
all articles with figures and tables.  |
|
Vol.50 |
|
