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The first characteristic of MCL is that it
is a chip technology that connects chips
through microbumps. Sony developed a
technology for connecting pairs of chips
without damage in which a few thousand
microbumps with a diameter of approximately
30 μm are distributed over the active
area of the LSIs and the chips are
connected by fusing them to form low-load
connections.
Figure 2 presents an MCL process flow
example using a logic chip and a memory
chip. After the wafer process has completed,
microbumps are formed on the
logic wafer and the memory wafer, wafer
testing is performed, and thinning/dicing
are performed.
Then, just the chips that passed testing are
selected and the singularized (diced) logic
and memory chips are joined (Chip on
Chip connection).
After that, underfill is injected between
the chips and the chips are packaged. Finally,
testing completes the process.
Photograph 1 is a scanning electron microscope
(SEM) image taken from the top
of the microbumps formed on the active
area of a chip. The microbumps are
formed by electroplating with a lead-free
solder (SnAg). To facilitate multi-pin connection
and high-speed transfers, the
microbumps are approximately 30 μm in
diameter and have a minimum pitch of
60 μm. Figures 3 and 4 are diagrams of
Chip on Chip connection using
microbumps. The microbump arrays
formed on the chip surfaces are placed
face-to-face in a bonder, positioned, and
then fused with heat and pressure. Issues
of concern with respect to this connection
technology include not only joining
hemispherical bumps with an extremely
small radius of curvature with minimal
misalignment and furthermore without
causing electrical or mechanical damage
to the chips but also controlling the gap
between the joined chips with high precision.
To satisfy these requirements, we set the
load used for bonding to the extremely
low load of under 0.1 gf/bump*1 and we
optimized the temperature, load, and heating
profiles during bonding. As a result
we achieved a post-bonding gap of approximately
25 μm between the chips and
a misalignment of less than 3 μm (average
+ 3σ).
In the next process, underfill is injected
in the gap between the chips. The underfill
process makes use of the capillary
phenomenon to fill the gap between the
chips with resin with no voids. The underfill
must provide protection to the
bumps to increase the reliability of the
connection. Low dielectric (low-k) films
with strengths lower than those of current
SiO2 films are used in 90 nm generation
and later generation LSIs, and protection of these films is also required of the underfill
process. Although these are competing
requirements, we focused on the
physical properties of the material, such
as the glass transition temperature and the
coefficient of expansion, developed materials
and optimized the injection
method, and were able to establish an
underfill injection technology that meets
these conflicting requirements.
Figure 5 shows a cross sectional SEM
photograph of an MCL microbump connection
created using this process technology.
The corresponding pairs of
microbumps are fused together and underfill
is injected in a manner that prevents
void formation.
At the same time as achieving excellent
electrical characteristics in which the resistance
of each microbump is about 10
mΩ and the capacitance is about 50 fF,
this technology assures high reliability.
*1 In the current connection method using gold
bumps, a load of over 10 gf per bump was
required.
Photograph 1 Microbump Photograph
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Chip on Chip Connection
Technology Using Microbumps
Vol.50