The Development of Multiple
Strained Silicon Technologies |
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We developed technologies that apply ideal
three-dimensional stresses to the channel area
by combining multiple strained silicon technologies.
Figure 1 Stress Direction for Increased Transistor Carrier Mobility
The <110> axis channel direction for the silicon (100) plane
What is Strained Silicon
Technology?
When a stress is applied to a silicon crystal,
the lattice constants change. Along with that
change, the energy levels and the carrier effective
mass change as well. Strained silicon
technology increases the transistor drive current
by applying stress to the device to increase
mobility. However, since the direction
of stress application required to increase
mobility differs depending on the axial direction
and crystal plane orientation of the
silicon substrate and the type of carrier, stressors
must be embedded in the transistor so
that an ideal stress direction is achieved. (See
figure 1.) The stress provided by the stressors
used is on the order of a few GPa, and
the silicon atom spacing is changed by 1 to
2%. Since the pressure at the deepest part of
the Marianas Trench is said to be about 0.1
GPa, the pressure applied by this technology,
about ten times larger than that, is truly enormous.
The Introduced Strained
Silicon Technology
In this development project, we embedded
the following four stressors during the LSI
manufacturing process. First, we developed
a technology (i) that embeds a material that
has a tensile stress for device isolation. Since
it is necessary to apply stress in the opposite
directions to nMOS and pMOS devices in the
X and Z directions, we created different stressor
structures in the process that completes
the transistor structure. In particular, (ii) we
applied compression stress in the X direction
in the channel region by growing epitaxially
SiGe layer, which has lattice constants larger
than those of silicon, in the pMOS device
source/drain diffusion layer. Next, we developed
technologies that create the following
stressing films: (iii) a tensile stress film that
covers the nMOS electrode and (iv) a compressive
stress film that covers the pMOS
electrode. (See figure 2.) With these technologies,
we achieved a 20% increase in current
in the nMOS and a 60% increase in the
pMOS devices. (See figure 3.) Thus we succeeded
in acquiring the performance required
in the 45 nm generation CMOS transistors. |
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| Introducing Pores into the
Low-k Film |
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To reduce LSI power consumption and increase
the operating speed, we introduced
porous low-k film as inter-/intra layer dielectrics
for the 45 nm generation and thus reduced
the effective relative permittivity by
10% compared to the 65 nm generation. This
porous low-k film which has tiny holes in it,
is more easily damaged during plasma processing
than the conventional low-k film and
has a higher hygroscopicity. Since in general,
low-k films are hydrophobic, they do
not absorb moisture unless water is forcibly
enclosed. However, if they are damaged in
plasma processing hydrophilic surfaces may
be formed and water can diffuse into and accumulate
in the film. (See figure 4.) Although
the moisture absorbed in the low-k film is
degassed during thermal processing, if any
remains after metal wiring formation, the
metal wire may be corroded and electrical
performance may be degraded.
Therefore the most important issue in the porous
low-k process is how to reduce damage
during plasma processing. At Sony in the 65
nm generation, the etching damage (particularly
the influence of the plasma during resist
removal) was reduced by adopting a hybrid
structure consisting of PAr (polyarylene)
and SiOC films. In the 45 nm generation, in
addition to these, we newly developed a porous
low-k film formation procedure (see figure
5) and aimed at improving resistance to
the etching damage. |
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| Operational Verification of Ultrahigh-Density SRAM
with the Industry’s Smallest Cell Size, 0.25 μm2 |
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By taking full advantage of immersion lithography
technology (see figure 6) to precisely
process fine patterns, we developed SRAM
memory cells with a cell size under 0.25 μm2.
(See figure 7(a).) It is the butterfly curves that
visually express whether or not the data stored
in the SRAM cell is read out in a stable manner.
The larger the area enclosed by two lines
of the same color, the more stably data can
be read out. (See figure 7(b).) |
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Vol.48 |
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