Barriers to Scaling and the Corresponding Breakthroughs

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Since the CMOS LSI first appeared, its performance has been constantly improved by scaling down to smaller sizes and reducing the power supply voltage. Along with cost reductions due to reduced chip feature sizes, these scaling rules have become the foundation that supports both the evolution of logic LSIs, such as CPUs, and the electronics industry. Recently, three enormous barriers to the progress of this scaling have arisen. Thus it became necessary for us to overcome these barriers with new technologies during development of the 45 nm generation. Barriers and Breakthroughs 1 Increased leakage current (1) Increased off current Although the scaling rules call for the voltages that become the on/off thresholds to fall as the supply voltage falls, in the 45 nm generation, if the threshold voltage were reduced according to the rules, the transistor off state would become inadequate and a current comparable to the operating current would flow in standby mode. (2) Limits to thinning of the gate insulator The success of today’s CMOS technology is due to the fortunate fact that silicon oxide can form a superlative insulating film. In the 50 years since the birth of the CMOS LSI, performance has been improved by making this gate insulator thinner and thinner. However, the gate insulator film, which reached the 1 nm level in the 65 nm generation, already has a thickness of only about 5 atomic layers. If this film is made even thinner, quantum effects result in electric charge passing through the insulator causing the standby current to rise rapidly. To achieve the targeted performance improvements while avoiding these issues, we developed a strained silicon technology that achieves performance improvements without depending on threshold voltage reduction and gate insulator thinning that follows earlier scaling rules. Barriers and Breakthroughs 2 Increased wiring capacitance due to smaller design rules The scale down in design rules increases the wiring capacitance between adjacent lines. This cancels the effects of reduced load capacitance and gets in the way of improving the characteristics. To reduce the wiring capacitance, low-k materials such as fluorine or carbon doped oxide have been used as inter-/intra layer dielectrics. However, it is difficult to continue to reduce the dielectric constant in a stable manner in an insulating material. Therefore, for the 45 nm generation, we introduced pores in the low-k film to reduce the wiring capacitance. Barriers and Breakthroughs 3 Limits to scaling from optical lithography While reduced feature sizes in CMOS LSIs has been achieved by developments in lithography technology based on using shorter light wavelengths, development of lithography technologies using wavelengths shorter than that of the ArF laser (193 nm) introduced at the 90 nm generation have been delayed. In this work, we inserted water between the pattern exposure lens and the silicon wafer and used the index of refraction of water to improve the resolution for the circuit pattern. As a result of this, we achieved an SRAM cell size with an area reduced by 50% from that of the 65 nm generation.