Prototype Chip |
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Figure 6 shows a photograph of this prototype
CMOS sensor chip. It supports an
optical size with a diagonal of 8.7 mm
(Type 1/1.8) and has a chip size of 7.0
(H) mm × 5.2 (V) mm. A 0.18 μm rule
single polysilicon layer/three metal layer
CMOS process is used.
Photograph 1 shows a sample image taken
at 180 frame/s. The noise levels in this
CMOS sensor that uses the column-parallel
A/D conversion technique are almost
the same at 180 frame/s and 45 frame/s.
There is almost no recognizable image
degradation when switching from 45
frame/s to 180 frame/s. Also, although the
image distortion due to the focal plane
shutter, which is a characteristic of CMOS
sensors can be seen in the image taken at
45 frame/s, this distortion is almost invisible
in the image taken at 180 frame/s.
(See photograph 2.) |
Figure 6 Chip Layout (Prototype)
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Future Developments |
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The column-parallel A/D conversion
technique introduced in this article
achieves radical improvements in the
speed and picture quality of CMOS
sensors. Sony is now developing CMOS
sensors that adopt this technique and take
maximum advantage of CMOS sensor
high-speed characteristics for application
such as seamless imaging that can capture still images at the same time as capturing
moving images to hard disk video
recorders and other devices. This technology
also has the possibility of implementing
new ultrahigh-speed cameras that can
capture video at the ultrahigh speed of
several hundred frame/s.
Sony is now developing products that aim
at creating a new imaging world by combining
the high sensitivity and high picture
quality technologies created during
Sony’s CCD development efforts with the
high-speed imaging technology that
CMOS sensors can achieve. Keep your
eye on Sony’s ultrahigh-speed high picture
quality CMOS sensors. |
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all articles with figures and tables.  |
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Vol.47 |
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