The Column-Parallel
A/D Conversion Technique |
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The possibility of system integration is a
major feature of the CMOS sensor technology.
It is possible to integrate both
analog and digital circuits on the same
chip as the pixel array used to capture
images. Conventional CMOS sensors
implemented noise cancellation using
analog CDS circuits, and furthermore provided
digital outputs by integrating A/D
converters on the same chip. (See figure
1.) An amplifier device is embedded in
each pixel in the CMOS sensor pixel
circuit, and light is converted to an electrical
signal by amplifying the signal charge generated by photodiode optoelectronic
conversion. The pixel electrical signals
selected by the vertical scan circuit
are read out over the vertical signal lines.
Since the signal is amplified at the pixel
in the pixel structure that includes an
amplifier, it is possible to design sensors
in which the signal is relatively immune
to the influence of noise on the signal path.
On the other hand, since each pixel has
its own amplifier, variations in device
characteristics between pixels do occur.
These variations are removed using a CDS
circuit that samples both the reset state
signal and the data signal and subtracts
them. In the conventional circuit structure,
the pixel signal from which the noise has
been cancelled is temporarily stored in a
memory capacitor. The analog signals
stored in the CDS circuit are sequentially
read out by the horizontal scan circuit and
converted to digital signals by A/D converters
integrated in the device. Until now,
CMOS sensor functionality has been significantly
improved by integrating the
analog CDS circuits and the A/D converters
on the same chip along with the CMOS
sensor itself.
At the same time, however, the following
problems occur in conventional CMOS
sensors. Although the fixed pattern noise
between pixels can be removed by the
CDS circuits located at each column, a
vertical form of fixed pattern noise occurs
due to differences between the CDS
circuits themselves.
Also a capacitor with a size larger than a
certain value is required in the CDS
circuit to record and hold the post-CDS
signal, and this results in an increase in
the area of this circuit. Furthermore, the
recorded and stored analog signals are
easily influenced by switching noise in the
high-frequency band due to the horizontal
transfer operations.
To resolve these problems, Sony adopted
the column-parallel A/D conversion technique.
(See figure 2.) Since each column
has its own A/D converter in the column-parallel
A/D conversion technique, the
analog signals read out from the vertical
signal lines can be A/D converted directly.
Since the analog signals are A/D converted
directly without first recording and
storing, the capacitors that take up chip
area as circuit structural components are
no longer required. Also, the analog CDS
circuits used for noise cancellation are no
longer required. The CDS operation
previously performed with analog signal
processing is now performed with digital
processing. This technique makes it
possible to perform high precision noise
cancellation that is not dependent on
variations in the CDS circuits.
Another advantage of the column-parallel
A/D converter technique lies in its conversion
speed. Since processing is performed
in parallel for each column, the
A/D conversion frequency is extremely
low, and the high-frequency band noise
components can be separated from the
signal components. This means that even
if the number of pixels or the frame rate
are increased, high picture quality digital
signals with extremely low noise can be
acquired.
A column-parallel A/D converter CMOS
sensor consists of the following six components.
1. Pixel array
2. Vertical scan circuit
3. Column-parallel A/D converter
4. D/A converter that generates a ramp wave
5. Logic control block
6. Digital output LVDS interface
Figure 3 shows the block diagram for the
column-parallel A/D converter CMOS
sensor. The CMOS sensor shown here
operates from a single 75 MHz master
clock. An internal PLL circuit generates
a 300 MHz high-speed clock that is four
times the frequency of the master clock
to implement the high-speed operation of
the column-parallel A/D converter, the
slope generating D/A converter, and the
LVDS interface. |
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Column-Parallel Digital CDS
Technique |
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In the Sony-proposed column-parallel
CDS technique, digital dual sampling
(digital CDS) using the high-speed clock
makes both high-speed readout and high
picture quality possible. The column-parallel
A/D converter consists of comparators
and counters. (See figure 4.) The comparators
in each column compare the ramp
wave generated by the D/A converter with
the pixel output. The counters in the columns
are implemented as ripple counters
and count the number of clocks until the
comparator output changes. The subtraction
of two digital signals can then be
implemented by counting down during the
reset state signal period and counting up
during the data signal period. The digital
CDS uses the high-speed 300 MHz clock
and shortens the A/D conversion sampling
period.
The column-parallel digital CDS technique
operating sequence is as follows.
(See figure 5.)
1. Pixels are reset and the pixel reset state signal
is output to the vertical signal lines.
2. PLL clock cycles are counted until the
ramp wave matches the pixel output and a
reset state signal A/D conversion is performed.
Here the ripple counter is set to
decrement count operation by the up/down
switching signal.
3. Data signals are output from the pixels. At
this point, the ripple counter is set to increment
count operation by the up/down
switching signal.
4. An A/D conversion of the same type as that
of step 2 is performed and as a result the
counter output indicates a value that is the
value of subtracting the reset state signal
from the data signal (digital CDS). Signals
read out from the pixels are processed in a
column-parallel manner.
5. The digital CDS operation terminates and
the digital data is transferred to the latch
circuit that is present in each counter block.
This allows the A/D conversion of the next
row and the horizontal data transfers to be
performed in a pipelined manner. |
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