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ASC9: 90 nm CMOS Process
Technology
The Industry’s First Practical 90 nm Embedded
DRAM Process |
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The industry's most advanced process features 90 nm design rules |
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Low-k dielectric and copper wiring |
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High-density embedded trench DRAM |
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Three times the operating speed and one-third the power consumption of 0.18 µm technologies |
•Figure 1 Sony's Embedded
DRAM Progress |
•Figure 2 Process Technology
Roadmap |
Sony has been working on developing
embedded DRAM logic processes since the 0.5 µm
generation. Initially, the main target of this
technology was miniaturization and lower power
in AV products such as camcorders and MD players.
However, in the 0.25 µm generation, Sony
targeted developing higher bandwidth and Sony
Computer Entertainment Corporation adopted this
technology in the “Graphics Synthesizer®
graphics processor used in the PlayStation®2 product.
(See figure 1.)
Now, Sony, in cooperation with Toshiba Corporation,
has jointly developed the ASC9 embedded DRAM process
based on a 90 nm CMOS process featuring line widths
approximately 1/1000 the width of a human hair.
Sony established this 90 nm process more than
6 months in advance of the predictions of the
International Technology Roadmap for Semiconductors
(ITRS), a technology standard for the industry.
Normally, first practical application of embedded
DRAM technologies trail ITRS predictions by about
a year. (See figure 2.) This article presents
an overview of this process technology.
* PlayStation, Emotion Engine, and Graphics Synthesizer
are registered trademarks of Sony Computer Entertainment
Corporation. |
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Development Concepts |
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Recently, many semiconductor manufacturers are focusing on SoC (system on chip) and, in particular, embedded DRAM technologies. While it goes without saying that these technologies are of particular use in high-speed applications that generate wide bandwidths, they also can be of great value in low-power applications such as portable equipment since they can eliminate the power lost in driving external DRAM bus.
Sony released its first SoC product that included 0.50µm generation embedded DRAM in 1995. In products starting with the next generation, the 0.35μm genera-tion, the approach was not to add DRAM after the logic, but rather to develop an embedded DRAM process from the start.
The DRAM of the 90 nm generation CMOS process ASC9 described in this article has the deep trench cell, which has a plain surface and is suitable for combined with logic. Furthermore, this enables the logic circuits to achieve the same characteristics as those of leading edge logic technologies, despite being combined with DRAM. (See figure 3.) The transistors achieve a high-level balance between high speed and low power due to the 70 nm line width fabrication technology used. Low-resistance copper wiring and low dielectric constant dielectric film (k = 2.96) are used for the wiring. As you can see, this process takes maximum advantage of the latest technologies. |
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High-Performance Trench Capacitor Embedded DRAM |
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| Trench capacitor DRAM was selected for the ASC9 process since it is possible to create high-performance transistors with this technology. MOSFETs are formed after the trench capacitors have been formed. This means that the additional thermal processing of DRAM processes is not applied to these transistors, allowing the process to achieve performance equivalent to pure CMOS processes that do not include embedded DRAM. This DRAM features a high density with a 0.19μm2 cell; up to 256 Mbits of DRAM can be embedded with logic circuits. The state-of-the-art technology, in which trench capacitors with 0.2μm in diameter are etched to a depth of 8μm, assures a capacitance of 40 fF, thus achieving data retention time equivalent to commodity DRAM. The upper section of the trench capacitor is perfectly flat, allowing the following transistor formation processes to proceed in exactly the same manner as when DRAM is not embedded with logic.(See figures 4 and 5.) |
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High-Performance MOSFET |
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Sony developed the logic
core transistors in this process focusing on a
balance between high speed and low power. The
ASC9 process transistors achieve three times the
operating speed and one-third the power consumption
of the ASC7 process (0.18µm). (See figure
6.) The ASC9 process incorporates the latest technologies,
including 70 nm gate line width fabrication technology,
ultra shallow junction formation technology, and
Co salicide*1 formation technology.
(See figure 7.) Increased standby current due
to leakage currents has become a critical problem
for the latest fabrication technology transistors.
As is the case with tran-sistors up to the previous
generation, subthreshold leakage*2
control is important. Sony has adopted extremely
low energy ion implantation and spike RTA technologies
in the ASC9 process. In addition, suppressing
gate direct tunneling*3 is a new problem
that is now seen as important. To acquire a high
drive current at the low voltage of 1.2 V in ASC9,
an extremely thin 1.7 nm gate dielectric film
is used. Plasma nitridation is used to achieve
both high drive current and low gate leakage while
maintaining high reliability. Furthermore, to
allow the ASC9 process to support as wide a variety
of product needs as possible, three Vth options,
0.2 V, 0.3 V, and 0.4 V, are provided in the ASC9
core transistors. By using these different tran-sistors
in appropriate ways, applications can meet the
conflicting needs of high speed and low power
at the same time by only using high-speed transistors
in places where they are required, and using low-power
transistors in circuits that only need to operate
at lower speeds. In addition to the core transistors,
1.8 V, 2.5 V, and 3.3 V transistors are also provided
for I/O and analog applications. The 2.5 V transistor
is also used in the DRAM.
*1 Co salicide: An alloy of cobalt and silicon. This material has a lower resistance than the Ti salicide used in the 0.18μm process.
*2 Sub-threshold leakage: Leakage current that flows when the transistor is in the off state.
*3 Direct tunneling: Refers to current that flows due to quantum effects when the dielectric film is thin. |
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Low-k and Cu Wiring |
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As finer design rules are
used, the width of the interconnects becomes narrower,
the resistance increases, and the delay in transmission
of the electrical signals increases. To resolve
this problem, the aluminum (Al) that was used
in the earlier ASC7 process has been replaced
with copper (Cu) in this process as the interconnect
material. Also, since the spacing between interconnects
is reduced, the interconnect capacitance is increased,
and this also contributes to increased delay in
transmission of electrical signals. The ASC9 process
uses a low-k (low dielectric constant) film*4
with an added organic material for the earlier
silicon oxide film. (See figure 8.) Sony optimized
the interconnect dimensions not only for transmission
delay, but also for crosstalk by taking full advantage
of high-level simulation technologies. This process
allows up to 11 layers of interconnects to be
used. Although earlier processes formed the vias
and the interconnects separately (see figure 9),
ASC9 uses dual damascene processing technology
to form them at the same time. (See figure 10.)
Although extremely high-level technologies are
required to use low-dielectric constant films
with dual damascene, Sony adopted this difficult
technology to reduce costs.
*4 Low-dielectric constant film: A film with a lower dielectric constant used to reduce parasitic capacitance. Compared to the conventional silicon oxide film, these films have lower mechanical strengths and thus require high-level fabrication technologies. |
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Future Developments |
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| The superb performance of this newly-developed ASC9 process (a 90 nm CMOS process) will become a powerful driving force towards the creation of new and attractive products in a wide range of categories including AV, IT, and game products. Sony will also deploy the technologies and know-how developed here to a wide range of other processes, such as RFCMOS and CMOS image sensors. Furthermore, progress is already underway on the next generation 65 nm process, as has already been reported in an earlier CX-NEWS. Keep your eye on Sony, the world leader in semiconductor technologies. |
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See all articles with figures and tables.  |
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Vol.34 |
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