Hybrid Dual Damascene |
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| Hybrid dual damascene is a process for
conductor formation that simultaneously forms wiring
and contact holes (via) on an interlayer insulation
film formed from a layer structure of low dielectric
constant films with differing characteristics. Figure
2 shows a cross section of the hybrid dual damascene
device structure. Its major features are that it adopts
a layered low dielectric constant film structure that
uses an organic film called polyarylether (PAE) as
the interconnect insulation film and a carbon-doped
silicon oxide (SiOC) inorganic insulating film as
the interlayer film in which the contact holes are
formed, and that it forms the embedded wiring using
copper, which has a lower resistance than aluminum,
as its main material. Sony focused on this hybrid
dual damascene structure as a process that holds hope
for improvements in both shape control characteristics
and sample-to-sample variations in device characteristics
as compared to the previous generation. |
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Target Wiring Performance and Low
Dielectric Constant Film Structure |
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Figure 3 shows the result of simulating
the wiring capacitance for various low dielectric
constant film structures. A capacitance increase of
approximately 12% due to the reduced interconnect
spacing (140 to 100 nm) is expected if the carbon-doped
silicon oxide/nitrogen-dop
ed silicon carbide (SiOC/SiCN)
film structure used in the wiring process in the previous
generation are applied in the finer wiring fabrication
of the 65 nm generation. However, a capacitance reduction
of approximately 15% from that of the previous generation
is required in the 65 nm generation. Sony developed
a porous organic film (porous PAE) with an optimized
pore density and a second-generation SiOC/SiC layered
process as a hybrid low dielectric constant film structure
that can achieve the target performance.
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Dual Damascene Formation Methods |
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Sony developed the triple hard mask
method as the new dual damascene formation method
that supports the fine pattern formation required
by the 65 nm generation. Figure 4 shows the layered
PAE/SiOC film hybrid dual damascene formation method.
As compared to the conventional dual hard mask method,
the triple hard mask method has the following advan
tages.
1. It improves the degree of contact hole fine fabrication
precision to a level that can support the 65 nm generation
by reducing the step height of the hard mask.
2. It makes easier to open holes in the SiOC film
between contact hole interconnect. Photograph 1 shows
the manufactured morphology of PAE/SiOC hybrid dual
damascene fabricated using the triple hard mask method.
Introducing this process allowed Sony to achieve a
PAE/SiOC structure fine dual damascene fabrication
that would have been difficult with conventional dual
hard mask methods. In addition, Sony developed the
following technologies: low dielectric constant film
formation optimal for a hybrid structure that can
support the 65 nm generation, WET (postprocessing),
copper embedding, and copper chemical/mechanical polishing,
and also integrated these technologies into the fabrication
process.
Photograph 2 shows the cross section of the completed
hybrid dual damascene copper wiring. This photograph
proves that this method can form 100 nm half-pitch
multilevel wiring with excellent morphology for the
first time in the industry. |
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Wiring Characteristics and Reliability |
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| Table 2 presents representative electrical
and reliability characteristics for PAE/SiOC hybrid
dual damascene copper wiring. Sony verified that this
process produces low-resistance high yield wiring
and contact hole conductance characteristics with
minimal sample-to-sample variations. Sony was also
able to prove that this technology produces multilevel
wiring with excellent resistance to heat for the thermal
histories expected in the wafer process. |
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Superiority of Hybrid Dual Damascene |
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| Table 3 presents the results of comparing
the multilevel wiring structures a
ssumed for the 65
nm generation. In addition to this newly-developed
hybrid process, Sony also considered adopting the
dual damascene structure that uses a single low dielectric
constant film or the single damascene structure in
which contact holes and wiring are formed separately.
Based on a comprehensive evaluation of wiring performance,
ease of implementation, and cost, of all these structures,
the hybrid dual damascene structure is currently seen
as the optimal process as a solution for the issues
expected to face the 65 nm generation. |
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Future Development |
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| Sony is now engaged in process optimization
for the start of mass production, aiming at the completion
of development by spring 2004 for 65 nm generation
ultrahigh speed embedded DRAM logic. Sony also hopes
to apply this leading-edge process module that includes
multilevel wiring technologie
s to CMOS derived devices
in addition to embedded DRAM logic. Sony is committed
to continuing to contribute to the creation of new
process solutions. Keep your eye on Sony for the latest
CMOS process technologies. |
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See all articles with figures and tables.  |
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Vol.33 |
