Timing Recovery

Unlike LVDS based data interfaces, GVIF does not need a separate cable to transport the clock from the transmitter to the receiver (see Figure 3-2). Clock information is derived from the data itself at the receiver, making use of an on-chip PLL and a cooperative reference signal that is upon start-up sent from the transmitter. This approach eliminates the need for extra cabling or for off-chip circuitry to create the received data clock. At the same time it also gives GVIF enabled devices a hot-plugability feature. The GVIF receiver makes use of a common-mode voltage on the differential cable to acknowledge cable-driver status, and the transmitter temporarily sends reference signals to help the receiver PLL to achieve lock. Figure 4-3 shows a block diagram of the clock and data recovery circuit common to GVIF devices.

Figure 4-3: Clock and Data Recovery Circuit

A GVIF system can support operation over a wide shift clock frequency range, from 8 MHz though as high as 65 MHz in some cases.