GVIF Technology Elements
Figure 4-1 presents a high level block diagram of a GVIF transmitter/receiver pair showing the major technology blocks. These blocks include an optional HDCP encrypter/de-encrypter, an encoder/ decoder paired with a high speed serializer/deserializer (serdes or multiplexer/demultiplexer), an automatic clock and data recovery (CDR) circuit, and an adaptive equalizer. An additional element of the system is the cable, which must meet reasonable requirements for signal loss, intra-pair skew, and impedance matching. A detailed description of HDCP is out of the scope of this white paper, but can be found at the following web site: http://www.digital-cp.com/home.The following sections provide additional details on the remaining technology elements.
Figure 4-1: GVIF Transmitter/Receiver Generic Block Diagram
GVIF Encoder/Decoder and Mux/Demux
GVIF's encoder/decoder translates 24-bit RGB data and 4-bit synchronization/control signals into a 30-bit word for serial NRZ data transmission. The encoding scheme is optimized to insure the following:
- minimize DC offsets on differential data lines
- create sufficient serial data transitions to insure proper operation of the receiver's clock and data recovery circuit
- allow for transmission of control signals during the non-blanking interval
Careful attention to DC balance is required to allow for AC coupling of the received data line. Although the RGB pixel data will generally change frequently, it is also possible for long periods of constant data to be transmitted (for example, a black screen image) which could cause a significant non-zero average voltage in the transmitted data stream. The GVIF encoder thus has two modes, both of which create a 30-bit code as shown in Figure 4-2. In the case of static control signals, the encoder creates a 30-bit data stream that has sufficient alternating transitions to insure nearly zero DC offsets from the RGB pixel data only. Such a scenario would normally apply during the period when the display is enabled. However, it is also possible for the designer to send synchronous/control data during the active display period as shown in the second part of Figure 4-2. The advantage of this is that it provides for a reduced blanking interval and therefore faster supported frame rates. A third option (not shown) is to use the blanking interval to make use of the 24-bit normally assigned to RGB pixel data to send additional control, audio, and other data as needed. This data would be packetized and sent at an effective packet rate equivalent to the video horizontal or vertical frame rate.
Figure 4-2: GVIF Data Encoder Operation